1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for fabricating the nonvolatile semiconductor memory device, and in particular, to a NOR-type nonvolatile semiconductor memory device and a method for fabricating the NOR-type nonvolatile semiconductor memory device.
2. Description of the Related Art
Recently known nonvolatile semiconductor memory devices include memory cells of a gate structure in which a floating gate and a control gate are stacked to enable data to be electrically rewritten. With a reduction in the size of the memory cells in these nonvolatile semiconductor memory devices, the magnitude of capacitive coupling between adjacent floating gates tends to increase. This disadvantageously varies a threshold voltage for the memory cells. To solve this problem, for example, Jpn. Pat. Appln. KOKAI Publication No. 2003-188287 proposes, for example, a nonvolatile semiconductor memory device having a shield electrode between the memory cells to reduce the capacitive coupling between the floating gates.
In the nonvolatile semiconductor memory device disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2003-188287, a single crystal silicon layer functioning as the shield electrode is formed on a source diffusion layer and a drain diffusion layer. The shield electrode is located as high as the floating gate. This structure effectively enables an increase in the distance between a word line (control gate) formed on the floating gate and the shield electrode. As a result, even if a high voltage is applied to between the word line and the shield electrode during data erasure, field intensity can be reduced. This makes it possible to inhibit the dielectric breakdown of an insulating film provided between the word line and the shield electrode.
On the other hand, the following problems may be involved in the formation of a shield electrode based on the epitaxial growth of a silicon layer on the source diffusion layer and drain diffusion layer. The reduced size of the area in which silicon is to be epitaxially grown frequently results in improper growth, which may cause the shield electrode to be inappropriately shaped, or inappropriate impurity diffusion, which may increase resistance. This prevents the shield electrode from exerting a sufficient shield effect. As a result, increasingly miniaturized semiconductor memory devices have made it difficult to suppress the capacitive coupling between the adjacent floating gates under the shield effect to inhibit a variation in threshold voltage.
The above problem occurs particularly frequently in NOR-type nonvolatile semiconductor memory devices employing a self-aligned-source (SAS) structure for a source area. The SAS structure enables the space between the memory cells sandwiching the source area between them to be minimized. However, this structure involves the formation of grooves, which results in high steps in a layer under the shield electrodes. Thus, an attempt to grow a silicon layer for the shield electrode on the source diffusion layer by a conventional method may lead to further improper growth owing to the step shape of the underlying silicon substrate. This may disadvantageously prevent the shield electrode from being appropriately formed.